In the semiconductor device industry, smaller and thinner devices are always desired. As sizes shrink, it can be challenging to provide high yield processes at low cost. For example, fan-out wafer level packaging (FOWLP) can suffer from yield loss due to die drift, mold cure shrinkage, and warpage. This may be exaggerated when multiple layers of redistribution metal are required to route the signal, power and ground from the semiconductor device to the final ball grid array pin or ball grid array solder ball. It is desirable to address these, and other challenges to small form factor semiconductor devices.